What Is the Working Principle of Macronix's MX25U1632FBHI02?
The MX25U1632FBHI02 is a 1.8V 16Mb serial NOR Flash memory launched by Macronix. It is internally organized as 2,097,152 × 8 bits, uses a WLCSP-8 wafer-level package, and supports SPI, Dual I/O, Quad I/O, and QPI protocols. Its maximum clock frequency reaches 133 MHz under all protocols. The core of its working principle lies in the coordinated operation of the serial peripheral interface protocol and the NOR Flash memory array.
I. Basic Principle of Data Storage
The chip uses NOR Flash technology. Each memory cell is composed of a floating-gate MOSFET. By injecting charge into or removing charge from the floating gate, the threshold voltage is changed, thereby achieving non-volatile data storage. The internal memory array is divided into uniform 4KB sectors, which can be further combined into 32KB or 64KB blocks. Any block can be erased individually. In single I/O mode, the memory organization is 16,777,216 × 1 bit; after switching to Dual I/O or Quad I/O mode, the organization becomes 8,388,608 × 2 bits or 4,194,304 × 4 bits, respectively, improving throughput through parallel transmission.
II. Communication Mechanism Between Host and Chip
The chip communicates with the host through a three-wire bus: clock input (SCLK), serial data input (SI), and serial data output (SO), enabled by the chip select signal CS#. In Dual I/O read mode, SI and SO become SIO0 and SIO1 respectively, enabling 2-bit parallel transmission. In Quad I/O mode, WP# and RESET# are further multiplexed as SIO2 and SIO3, enabling 4-bit parallel transmission. The chip supports SPI mode 0 (CPOL = 0, CPHA = 0) and mode 3 (CPOL = 1, CPHA = 1). Data is latched on the rising edge of SCLK and shifted out on the falling edge.
| Working Mode | Data Pins | Theoretical Throughput (133 MHz) |
|---|---|---|
| Single I/O SPI | SI, SO | 133 Mbps |
| Dual I/O | SIO0, SIO1 | 266 Mbps |
| Quad I/O | SIO0–SIO3 | 532 Mbps |
| QPI | SIO0–SIO3 | 532 Mbps |
III. Read, Write, and Erase Operation Flow
Read operation: After the host pulls CS# low, it sends a read instruction such as Fast Read 0Bh, followed by a 3-byte address and configurable dummy cycles. The chip outputs data bit by bit in subsequent clock cycles. The address counter automatically increments and wraps around at the highest address.
Program operation: The basic unit is a 256-byte page. The host first sends the Write Enable instruction (WREN) to set the WEL flag, then sends the Page Program instruction (PP, 02h), the target address, and data. The chip internally executes automatic program and verify algorithms. When finished, the WIP bit is cleared.
Erase operation: It supports 4KB sector erase (SE, 20h), 32KB block erase (BE32K, 52h), 64KB block erase (BE, D8h), and chip erase (CE, 60h/C7h). Erase is also completed by internal automatic algorithms.
IV. Status Monitoring and Protection Mechanisms
The chip has a built-in status register. The WIP bit indicates whether a program or erase operation is complete, the WEL bit indicates the write enable status, and the BP0–BP3 bits define the size of the protected area. In addition, it provides an Advanced Sector Protection mode, supporting non-volatile individual sector/block protection and software locking mechanisms, as well as an additional 8K-bit secure OTP area, effectively preventing accidental or malicious data modification.
Q: How does the MX25U1632FBHI02 increase read speed without adding pins?
A: By multiplexing SI, SO, WP#, and RESET# as SIO0–SIO3, it achieves 4-bit parallel data transmission in Quad I/O mode. It also supports configurable dummy cycles (4/6/8/10 cycles). The more dummy cycles, the higher the clock frequency limit. With a 10-cycle configuration, it can reach 133 MHz.
Q: Can the chip respond to read instructions during programming or erasing?
A: It cannot respond directly. However, the chip supports program/erase suspend and resume functions. The host can send a suspend instruction to interrupt the current operation, read data from other sectors, and then resume the operation.
In summary, the working principle of the MX25U1632FBHI02 can be summarized as follows: based on NOR floating-gate memory cells, it realizes command interaction and data transmission between the host and the memory array through the SPI/QPI serial interface protocol, completes data writing with internal automatic program/erase algorithms, and ensures operational reliability and data security through status registers and multi-level protection mechanisms.
